High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dies vertically and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance random access memory (DRAM) interface and vertically stacked DRAMs. FIG. 1A is a schematic diagram of a conventional HBM stack 11 including semiconductor chips, such as an I/F die (e.g. logic die) 12 and a plurality of core dies (DRAM dies) 13. The HBM stack 11 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 13 is coupled to two channels. In this example, the core dies 13a, 13b, 13c and 13d are coupled to channels A and C, channels B and D, channels E and G, and channels F and H, respectively. For example, a clock frequency, a command sequence, and data can be independently provided for each channel. FIG. 1B is a schematic diagram of a conventional HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The HBM stack 21 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 23 may include two channels. In this example, a stack group 24a having a stack identifier (SID) “0” includes the core dies 23a, 23b, 23c and 23d including channels A and C, channels B and D, channels E and G, and channels F and H, respectively. A stack group 24b having a stack ID (SID) “1” includes the core dies 23e, 23f, 23g and 23h including channels A and C, channels B and D, channels E and G, and channels F and H, respectively. Thus, a destination die among a plurality of core dies in each channel (e.g., core dies 23a and 23e of channel A) addressed in a command may be identified by the SID.
FIG. 2A is a wiring diagram of the conventional HBM stack 11 including the I/F die 12 and the plurality of core dies 13. The I/F die 12 of the HBM 11 stack provides interfaces 18a, 18b, 18e and 18f which provide signals on four input/output channels among the eight input/output channels, which function independently of each other. Memory arrays of the channel A, channel B, channel E and channel F of the core dies 13a, 13b, 13c and 13d may be coupled to the I/F die 12 via native input/output lines (IOs) 17a, 17b, 17e and 17f, respectively. For example, the native IOs 17a to 17f may be implemented as conductive vias. For example, the conductive vias may have a spiral structure. Each core die 13 may include a command circuit for each channel. For example, the core dies 13a to 13d may include command circuits 16a to 16d for channel A, channel B, channel E and channel F, respectively. Thus, clock signals, command signals and data signals for each channel may be transmitted independently and a plurality of data buses and their respective channels can operate individually.
FIG. 2B is a wiring diagram of the conventional HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The I/F die 22 of the HBM stack 21 provides interfaces 28a, 28b, 28e and 28f which provide signals on four input/output channels among the eight input/output channels of two stack groups. Memory arrays of channels A, B, E and F of the stack group 24a and memory arrays of channels A, B, E and F of the stack group 24b may be coupled to the same native input/output lines (IOs) 27a, 27b, 27e and 27f, respectively. For example, memory arrays of channel A of the core die 23a in the stack group 24a and memory arrays of channel A of the core die 23e in the stack group 24b may be coupled to the native IO 27a. Each core die 23 may include a command circuit for each channel. For example, the core dies 23a to 23d in the stack group 24a may include command circuits 26a to 26d for channel A, channel B, channel E and channel F, respectively. The core dies 23e to 23h in the stack group 24b may include command circuits 26e to 26h for channel A, channel B, channel E and channel F, respectively. Each command circuit 26 may detect the SID in a command, check whether the SID in the command matches with an SID of the stack group of the core die 23 including the command circuit 26, and decode the command. If the SID matches, memory access actions responsive to the command may be performed. For example, when the interface 28a transmits a command on the input/output line 27a, the command circuit 26a receives the command and check whether the SID in the command is “0”. The command circuit 26a processes the command if the SID is “0” and ignores the command if the SID is “1”. The command circuit 26e also receives the command and check whether the SID in the command is “1”. The command circuit 26e processes the command if the SID is “1” and ignores the command if the SID is “0”. Thus, clock signals, command signals and data signals for each channel on each die may be transmitted independently.